Intel announced today that they’ll be shipping the new Core 2-based Xeon 5100 series, codenamed Woodcrest, this week. The new server processor has been anticipated for quite a while now, so there’s not a lot of new news to report with the announcement. Even the pricing, which ranges from US$206 (in lots of 1,000) on the low end and $851 on the high end, has been approximately known since February.
As expected, the newly announced line runs on a 1333MHz frontside bus. The top-end Xeon 5160 sports a 4MB shared L2 cache, runs at 3GHz, and has a TDP of 80W. Current Xeon owners who’re running the Bensley platform, based on the Blackford MCH, will be able to drop the new Xeon into their existing setup.
DailyTech reports rumors that the new Xeons won’t be available in retail channels for at least another two weeks, so if you want to get your hands on one you’ll have to buy one of the systems that vendors should start announcing shortly.
Speaking of the new systems, my money is on Apple going with the mid-range Woodcrest processors in their PowerMac (or whatever they’ll call it) line. Conroe will show up in the iMac and Mac Mini.
What’s next for the server wars
Intel is clearly hurting the worst in the server market, so it makes sense that they’re releasing the new Xeons first. As will be universally pointed out today, the Xeon launch is Intel’s response to Opteron’s gains. The question is, will Woodcrest stop the defection of system vendors like Dell to the other side?
My answer is, not likely, at least in Dell’s case. As has been pointed out here at Ars before, Dell is planning to make the most of the price/performance war between AMD and Intel by playing both sides against each other. Furthermore, Dell can’t possibly be happy that Intel is sharing the deep discount love with just about everyone nowadays, so they’re probably not inclined to do anything but turn up the heat on the chipmaker. Thus I expect that Dell’s response to Woodcrest will be to roll out more Opteron systems.
Intel talks optimization
Intel’s Tokyo presentation included a general overview of optimization for Core 2. I’ve got the PowerPoint slides from that, and here’s an Intel-supplied picture of the Core 2 microarchitecture:
Intel’s Core 2 Microarchitecture
If you’ve seen the above diagram before, then you’ll notice that there’s a new number in there. From what I know, the Tokyo presentation is the first time that Intel has disclosed this much information about Core 2’s fetch and predecode phases:
18-deep instruction queue6 instructions can be written per cycle (by PreDecode)5 instructions can be read per cycleImplements a single “Macro-fusion” per cycleDelivers complete instructions to the Decode stage
I’ll probably find a few more new tidbits as I make my way through the presentation, and when I do I’ll drop them in this thread.
At any rate, there’s still no word on the exact dispatch port layout of the execution core, or the exact number and breakdown of Core 2’s pipeline stages. (
I realize that many sites claim that Core 2 has a 14-stage pipeline, and this may well be the correct number. But in spite of the fact that sites are using that number as if it’s a given, it is speculation that has not to my knowledge been confirmed by Intel.)
Update: I finally got around to watching Pat Gelsinger’s Stanford talk, and he says that Core’s pipeline is 14 stages. So there is official confirmation on that number, though this is the only place I’ve seen it.